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general description the MAX16930/max16931 offer two high-voltage, synchronous step-down controllers and a step-up preboost controller. they operate with an input voltage supply from 2v to 42v with preboost active and can oper - ate in drop-out condition by running at 95% duty cycle. the devices are intended for applications with mid- to high-power requirements that operate at a wide input voltage range such as during automotive cold-crank or engine stop-start conditions. the MAX16930/max16931 step-down controllers oper - ate 180 n out-of-phase at frequencies up to 2.2mhz to allow small external components, reduced output ripple, and to guarantee no am band interference. the switch - ing frequency is resistor adjustable. the fsync input programmability enables three frequency modes for optimized performance: forced fixed-frequency opera - tion, skip mode with ultra-low quiescent current (20 f a), and synchronization to an external clock. the devices also provide a spread-spectrum option to minimize emi interference. the MAX16930/max16931 are offered with an asynchro - nous step-up controller. this preboost circuitry turns on during low input voltage conditions. it is designed to pro - vide power to step-down controller channels with input voltages as low as 2v. the devices also feature a power-ok monitor and overvoltage and undervoltage lockout. protection features include cycle-by-cycle current limit and thermal shutdown. the devices are available in a 40-pin tqfn-ep package and are specified for operation over the -40 n c to +125 n c automotive temperature range. features s dual, 2mhz step-down controllers s preboost for operation to 2v s 180 out-of-phase operation s 50ns minimum on-time allows 3.3v output from car battery at 2.2mhz s 20a operating current s wide input supply range from 3.5v to 36v (with - out preboost) s resistor programmable frequency between 200khz and 2.2mhz s q 1% output-voltage accuracy: 5.0v/3.3v fixed or adjustable between 1v and 10v s current-mode controllers with forced continuous and skip modes s frequency synchronization input s supply overvoltage and undervoltage lockout s overtemperature and short-circuit protection s thermally enhanced 40-pin tqfn-ep package s -40 n c to +125 n c operating temperature applications pol applications for automotive power distributed dc power systems navigation and radio head units 19-6631; rev 1; 7/13 ordering information and selector guide appear at end of data sheet. for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX16930.related MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 in, ins, cs3p, cs3n, fb3, en1, en2, en3, term to pgnd_ ....................................... -0.3v to +42v cs1, cs2, out1, out2 to agnd ........................ -0.3v to +11v cs1 to out1 ........................................................ -0.2v to +0.2v cs2 to out2 ........................................................ -0.2v to +0.2v cs3p to cs3n ...................................................... -0.2v to +0.2v bias, fsync, fosc to agnd ............................. -0.3v to +6.0v comp1, comp2, bston to agnd ..................... -0.3v to +6.0v fb1, fb2, fselbst, extvcc to agnd .............. -0.3v to +6.0v dl_ to pgnd_ ..................................................... -0.3v to +6.0v bst_ to lx_ ........................................................ -0.3v to + 6.0v dh_ to lx_ .......................................................... -0.3v to + 6.0v lx_ to pgnd_ ....................................................... -0.3v to +42v pgnd_ to agnd .................................................. -0.3v to +0.3v pgood1, pgood2 to agnd.......... ............. ......-0.3v to +6.0v continuous power dissipation (t a = +70 n c) tqfn (derate 35.7mw/ n c above +70 n c)............ ...... 2857mw operating temperature range. ....................... -40 n c to +125 n c junction temperature range .......................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow)...................................... +260 n c tqfn junction-to-ambient thermal resistance ( q ja ) .......... 28c/w junction-to-case thermal resistance ( q jc ) .............. 1.7c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v in = 14v, v bias = 5v, c bias = 6.8 f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max unit synchronous step-down dc-dc converters supply voltage range v in normal operation 3.5 36 v t < 1s 42 with preboost after initial startup condition is satisfied 2.0 36 supply current i in v en1 = v en2 = v en3 = 0v 8 20 f a v en1 = 5v, v out1 = 5v, v en2 = v en3 = 0v, v extvcc = 5v, no switching 30 40 v en2 = 5v, v out2 = 3.3v, v en1 = v en3 = 0v, v extvcc = 3.3v, no switching 20 30 v en1 = v en2 = 5v, v out1 = 5v, v out2 = 3.3v, v en3 = 0v, v extvcc = 3.3v, no switching 25 40 buck 1 fixed output voltage v out1 v fb1 = v bias , pwm mode 4.95 5 5.05 v v fb1 = v bias , skip mode 4.95 5 5.075 buck 2 fixed output voltage v out2 v fb2 = v bias , pwm mode 3.234 3.3 3.366 v v fb2 = v bias , skip mode 3.234 3.3 3.4 output voltage adjustable range buck 1, buck 2 1 10 v MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
3 electrical characteristics (continued) (v in = 14v, v bias = 5v, c bias = 6.8 f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max unit regulated feedback voltage v fb1,2 0.99 1.0 1.01 v output overvoltage threshold fb rising +10 +15 +20 % fb falling (note 3) +5 +10 +15 feedback leakage current i fb1,2 t a = +25 n c 0.01 1 f a feedback line regulation error v in = 3.5v to 36v, v fb = 1v 0.00 %/v transconductance (from fb_ to comp_) g m v fb = 1v, v bias = 5v (note 4) 1200 2400 f s dead time MAX16930, dl_ low to dh_ high 35 ns MAX16930, dh_ low to dl_ high 60 max16931, dl_ low to dh_ high 60 max16931, dh_ low to dl_ high 100 maximum duty-cycle buck 1, buck 2 95 % minimum on-time t on(min) buck 1, buck 2 50 ns pwm switching frequency range programmable, high frequency, MAX16930 1 2.2 mhz programmable, low frequency, max16931 0.2 1 buck 2 switching frequency MAX16930atlt/v+, MAX16930atlu/v+ only 1/2f sw mhz switching frequency accuracy f sw MAX16930, r fosc = 13.7k i , v bias = 5v 1.98 2.2 2.42 mhz max16931, r fosc = 80.6k i , v bias = 5v 360 400 440 khz spread-spectrum range spread spectrum enabled 6 % fsync input fsync frequency range minimum sync pulse of 100ns, MAX16930 1.2 2.4 mhz minimum sync pulse of 100ns, max16931 240 1200 khz fsync switching thresholds high threshold 1.5 v low threshold 0.6 cs current-limit voltage threshold v limit1,2 v cs - v out, v bias = 5v, v out r 2.5v 64 80 96 mv skip mode threshold current sense = 80mv 15 mv soft-start ramp time buck 1 and buck 2, fixed soft-start time regardless of frequency 2 6 10 ms phase shift between buck1 and buck 2 180 lx1, lx2 leakage current v in = 6v, v lx_ = v in , t a = +25 n c 0.01 1 f a dh1, dh2 pullup resistance v bias = 5v, i dh_ = -100ma 10 20 i dh1, dh2 pulldown resistance v bias = 5v, i dh_ = +100ma 2 4 i MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
4 electrical characteristics (continued) (v in = 14v, v bias = 5v, c bias = 6.8 f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max unit dl1, dl2 pullup resistance v bias = 5v, i dl_ = -100ma 4 8 i dl1, dl2 pulldown resistance v bias = 5v, i dl_ = +100ma 1.5 3 i pgood1, pgood2 threshold p good_h % of v out_ , rising 85 90 95 % p good_f % of v out_ , falling 80 85 90 pgood1, pgood2 leakage current v pgood1,2 = 5v, t a = +25 n c 0.01 1 f a pgood1, pgood2 startup delay time buck 1 and buck 2 after soft-start is complete 64 cycles pgood1, pgood2 debounce time fault detection 8 20 40 f s internal ldo: bias internal bias voltage v in > 6v 4.75 5 5.25 v bias uvlo threshold v bias rising 3.1 3.4 v v bias falling 2.7 2.9 hysteresis 0.2 v external v cc threshold v th,extvcc extvcc rising, hyst = 110mv 3 3.2 v thermal overload thermal shutdown temperature (note 4) 170 n c thermal shutdown hysteresis (note 4) 20 n c en logic input high threshold 1.8 v low threshold 0.8 v input current en1, en2 logic inputs only, t a = +25 n c 0.01 1 f a preboost minimum on time ton bst 60 ns minimum off time toff bst 60 ns switching frequency f boost v fselbst = 0v, r fosc = 13.7k i 1.98 2.2 2.42 mhz v fselbst = v bias , r fosc = 13.7k i 0.4 0.44 0.48 current limit i limbst cs3p - cs3n 108 120 132 mv ins unlock threshold v ins,uv one-time latch during startup; preboost is disabled until the v ins rises above this threshold 1 1.05 1.1 v ins off threshold v ins,off battery rising and en3 high, preboost turns off if v ins is above this threshold 1.2 1.25 1.3 v ins on threshold v ins,on,sw battery falling and en3 high, preboost turns back on when v ins falls below this threshold 1.1 1.15 1.2 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
5 note 2: limits are 100% production tested at t a = +25 c. limits over the operating temperature range and relevant supply volt - age are guaranteed by design and characterization. typical values are at t a = +25 c. note 3: overvoltage protection is detected at the fb1/fb2 pins. if the feedback voltage reaches overvoltage threshold of fb1/fb2 + 15% (typ), the corresponding controllers stop switching. the controllers resume switching once the output drops below fb1/fb2 + 10% (typ). note 4: guaranteed by design; not production tested. electrical characteristics (continued) (v in = 14v, v bias = 5v, c bias = 6.8 f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max unit ins threshold undervoltage lockout v ins,uv battery rising and en3 high 0.325 0.35 0.375 v battery falling and en3 high, preboost turns off when v ins falls below this threshold 0.275 0.3 0.325 bston leakage current v bston = 5v , t a = +25 n c 0.01 1 f a bston debounce time fault detection 10 f s dl3 pullup resistance v bias = 5v, i dl3 = -100ma 4 8 i dl3 pulldown resistance v bias = 5v, i dl3 = +100ma 1 2 i feedback voltage v fb3 no load on boost output 1.1875 1.25 1.3125 v boost load regulation error 0mv < v cs3p - v cs3n < 120mv, error proportional to input current 0.7 %/a en3 threshold high threshold 3.5 v low threshold 2 en3 input current v en3 = 5.5v 7 14 f a term resistance i term = 10ma 70 150 i term leakage current v term = 14v, v en3 = 0v, t a = +25 n c 0.01 1 f a ins and fb3 leakage current t a = +25 n c 0.01 1 f a MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
6 typical operating characteristics (t a = +25c, unless otherwise noted.) no-load startup sequence (v fsync = 0v) MAX16930 toc01 2ms/div v bat 5v/div v out1 2v/div v out2 2v/div v pgood1 5v/div v pgood2 5v/div full-load startup sequence (v fsync = 0v) MAX16930 toc02 4ms/div v bat 5v/div v out1 2v/div i out1 2a/div v out2 2v/div i out2 2a/div v pgood2 5v/div v pgood1 5v/div quiescent current vs. supply voltage MAX16930 toc04 supply voltage (v) quiescent current ( a) 35 30 25 10 15 20 5 10 20 30 40 50 60 70 80 0 0 40 buck 1 extvcc = v out2 buck 2 extvcc = v out2 switching frequency vs. load current MAX16930 toc07 load current (a) switching frequency (mhz) 5 4 2 3 1 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 2.30 2.10 0 6 buck 2 buck 1 buck 1 efficiency MAX16930 toc05 i out1 (a) efficiency (%) 1.0e+00 1.0e-01 1.0e-02 1.0e-04 1.0e-03 1.0e-05 10 20 30 40 50 60 70 80 90 100 0 1.0e-06 1.0e+01 pwm mode skip mode extvcc = v out1 f sw = 2.2mhz l = 2.2h v bat = 14v v out1 = 5v extvcc = gnd extvcc = v out1 extvcc = gnd switching frequency vs. r fosc (MAX16930) MAX16930 toc08 r fosc (k) switching frequency (mhz) 25 15 20 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 10 30 v bias = 5v v bias = 3.3v quiescent current vs. temperature MAX16930 toc03 temperature (c) quiescent current ( a) 120 100 80 60 -20 0 20 40 -40 10 20 30 40 50 60 0 -60 140 v en1 = v bat v en2 = 0v extvcc = v out1 v en1 = 0v v en2 = v bat extvcc = v out2 buck 2 efficiency MAX16930 toc06 i out1 (a) efficiency (%) 1.0e+00 1.0e-01 1.0e-02 1.0e-04 1.0e-03 1.0e-05 10 20 30 40 50 60 70 80 90 100 0 1.0e-06 1.0e+01 pwm mode skip mode extvcc = v out2 f sw = 2.2mhz l = 2.2h v bat = 14v v out2 = 3.3v extvcc = gnd extvcc = v out2 extvcc = gnd MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
7 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) switching frequency vs. r fosc (max16931) MAX16930 toc09 r fosc (k) switching frequency (mhz) 140 150 160 40 50 60 70 80 90 110 120 130 100 0.3 0.4 0.6 0.5 0.7 0.8 0.9 1.1 1.0 0.2 30 170 v bias = 3.3v v bias = 5v load transient response MAX16930 toc11 400s/div v out1 100mv/div i out1 1a/div load dump MAX16930 toc14 load dump, pwm 100ms/div v pgood2 5v/div v bat 10v/div v out2 1v/div switching frequency vs. temperature MAX16930 toc10 temperature (oc) switching frequency (mhz) 80 100 120 0 -40 -20 40 60 20 2.05 2.10 2.15 2.20 2.25 2.30 2.40 2.35 2.00 -60 140 r fosc = 13.7k? external fsync transition MAX16930 toc12 400ns/div v lx2 10v/div v lx1 10v/div v fsync 2v/div slow v in ramp MAX16930 toc15 10s/div v pgood1 5v/div v pgood2 5v/div v bat 5v/div v out1 2v/div v out2 2v/div dips and drops MAX16930 toc13 40ms/div v pgood1 5v/div v bat 10v/div v out1 5v/div short-circuit response MAX16930 toc16 200s/div v pgood1 2v/div i out1 2a/div v out1 1v/div MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
8 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) output overvoltage response MAX16930 toc17 1s/div v pgood1 2v/div v out1 1v/div buck 2 load regulation MAX16930 toc19 i out_ (a) v out_ (v) 5 4 1 2 3 3.290 3.291 3.293 3.292 3.294 3.296 3.295 3.297 3.289 0 6 v fsync = v bias fb2 line regulation MAX16930 toc22 v sup (v) v out_ (v) 25 20 15 10 5 0.995 1.000 1.005 1.010 0.990 0 40 30 35 v out1 = 1.8v buck 1 load regulation MAX16930 toc18 i out_ (a) v out_ (v) 5 4 1 2 3 4.990 4.991 4.992 4.994 4.993 4.995 4.997 4.996 4.998 4.989 0 6 v fsync = v bias v out_ vs. temperature MAX16930 toc20 temperature (oc) v out_ (%nominal) 60 40 20 -20 0 -40 99.75 99.80 99.85 99.90 99.95 100.00 100.05 100.10 99.70 -60 140 80 100 120 v out2 v out1 extvcc = v gnd v fsync = v bias i out_ =0a minimum on-time (buck 1) MAX16930 toc23 200ns/div v bat 5v/div v out1 1v/div i out1 = 300ma fb1 line regulation MAX16930 toc21 v sup (v) v out_ (v) 25 20 15 10 5 0.995 1.000 1.005 1.010 0.990 0 40 30 35 v out1 =1.8v MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
9 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) minimum on-time (buck 2) MAX16930 toc24 200ns/div v bat 5v/div v out1 1v/div i out2 = 300ma boost enable MAX16930 toc26 2s/div v bat 5v/div v in 5v/div v sns 1v/div v bston 5v/div spectral energy density vs. frequency MAX16930 toc29 frequency (khz) output spectrum (dbv ) 480 400 380 440 460 320 360 340 320 0 20 10 30 40 50 -10 300 500 measured on the max16931atls/v+ cold crank (preboost on) MAX16930 toc25 400ms/div v bat 10v/div v in 5v/div v out1 5v/div v pgood1 5v/div v bston 5v/div v out2 5v/div v pgood2 5v/div lx waveforms MAX16930 toc27 200ns/div v lx1 5v/div i out1 = i out2 = 1a v lx2 5v/div v lxbst 5v/div spectral energy density vs. frequency MAX16930 toc30 frequency (hz) output spectrum (dbv ) 1.0m 1.1m 960k -5 0 15 20 25 5 10 30 35 40 -10 800k 1.2m measured at v out2 on the MAX16930atlu/v+ preboost load regulation MAX16930 toc28 i out_ (a) v out_ (v) 5 3 4 2 1 9.60 9.55 9.75 9.70 9.65 9.85 9.80 9.90 9.95 9.50 0 6 v bat = 7v spectral energy density vs. frequency MAX16930 toc31 frequency (mhz) output spectrum (dbv ) 2.2 2.4 2.0 -5 0 15 20 5 10 25 30 35 -10 1.8 2.6 measured on the MAX16930atls/v+ MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
10 pin description pin configuration pin name description 1 lx1 inductor connection for buck 1. connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate drive. 2 dl1 low-side gate drive output for buck 1. dl1 output voltage swings from v pgnd1 to v bias . 3 pgnd1 power ground for buck 1 4 cs1 positive current-sense input for buck 1. connect cs1 to the positive terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 5 out1 output sense and negative current-sense input for buck 1. when using the internal preset 5v feedback divider (fb1 = bias), the buck uses out1 to sense the output voltage. connect out1 to the negative terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 6 fb1 feedback input for buck 1. connect fb1 to bias for the 5v fixed output or to a resistive divider between out1 and gnd to adjust the output voltage between 1v and 10v. in adjustable mode, fb1 regulates to 1v (typ). see the setting the output voltage in buck converters section. 7 comp1 buck 1 error-amplifier output. connect an rc network to comp1 to compensate buck 1. 8 bias 5v internal linear regulator output. bypass bias to gnd with a low-esr ceramic capacitor of 6.8 f f minimum value. bias provides the power to the internal circuitry and external loads. see the fixed 5v linear regulator (bias) section. 9 agnd signal ground for ic tqfn MAX16930 max16931 top view 35 36 34 33 12 11 13 dl1 cs1 out1 fb1 comp1 14 lx1 cs2 fb2 comp2 pgnd 2 dl2 lx2 fos c fsyn c 12 bston 45 67 27 28 29 30 26 24 23 22 en2 en1 dl3 term cs3n cs3p pgnd1 out2 3 25 37 en3 ins 38 39 40 n.c. bst1 dh1 fb3 pgood1 in + fselbst 32 15 pgnd 3 bst2 31 16 17 18 19 20 pgood2 bias agnd extvcc n.c. 89 10 21 dh2 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
11 pin description (continued) pin name description 10 extvcc 3.1v to 5.2v input to the switchover comparator 11 in supply input. connect in to the output of the preboost. bypass in with sufficient capacitance to supply the two out-of-phase buck converters. 12 pgood1 open-drain power-good output for buck 1. pgood1 is low if out1 is more than 15% (typ) below the normal regulation point. pgood1 asserts low during soft-start and in shutdown. pgood1 becomes high impedance when out1 is in regulation. to obtain a logic signal, pullup pgood1 with an external resistor connected to a positive voltage lower than 5.5v. 13 fb3 preboost feedback input. connect fb3 to the center tap of a resistive-divider between the boost regulator output and term to adjust the output voltage. fb3 regulates to 1.25v (typ). see the setting the output voltage in boost converter section. 14 ins input voltage sense for preboost. the voltage at ins is compared to internal comparator reference. program the preboost threshold by using resistor-divider from bat to ins to term pin. 15 cs3p positive current-sense input for preboost. connect cs3p to the positive terminal of the current- sense resistor. see the current limit in boost controller and shunt resistor selection in boost converter sections. 16 cs3n negative current-sense input for preboost. connect cs3n to the negative terminal of the current- sense resistor. see the current limit in boost controller and shunt resistor selection in boost converter sections. 17 term ground switch. term opens when the voltage at en3 is logic-low. use term to terminate the preboost feedback and ins resistive divider. 18 dl3 preboost n-channel mosfet gate-drive output 19 pgnd3 power ground for preboost. all the high-current paths for the preboost should terminate to this ground. 20 pgood2 open-drain power-good output for buck 2. pgood2 is low if out2 is more than 90% (typ) below the normal regulation point. pgood2 asserts low during soft-start and in shutdown. pgood2 becomes high impedance when out2 is in regulation. to obtain a logic signal, pullup pgood2 with an external resistor connected to a positive voltage lower than 5.5v. 21, 38 n.c. no connection 22 fsync external clock synchronization input. synchronization to the controller operating frequency ratio is 1. keep f sync a minimum of 10% greater than the maximum internal switching frequency for stable operation. see the switching frequency/external synchronization section. 23 fosc frequency setting input. connect a resistor from fosc to agnd to set the switching frequency of the dc-dc converters. 24 comp2 buck 2 error amplifier output. connect an rc network to comp2 to compensate buck 2. 25 fb2 feedback input for buck 2. connect fb2 to bias for the 3.3v fixed output or to a resistive divider between out2 and gnd to adjust the output voltage between 1v and 10v. in adjustable mode, fb2 regulates to 1v (typ). see the setting the output voltage in buck converters section. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
12 pin description (continued) pin name description 26 out2 output sense and negative current-sense input for buck 2. when using the internal preset 3.3v feedback-divider (fb2 = bias), the buck uses out2 to sense the output voltage. connect out2 to the negative terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 27 cs2 positive current-sense input for buck 2. connect cs2 to the positive terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 28 pgnd2 power ground for buck 2 29 dl2 low-side gate drive output for buck 2. dl2 output voltage swings from v pgnd2 to v bias . 30 lx2 inductor connection for buck 2. connect lx2 to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate drive. 31 dh2 high-side gate drive output for buck 2. dh2 output voltage swings from v lx2 to v bst2 . 32 bst2 boost capacitor connection for high-side gate voltage of buck 2. connect a high-voltage diode between bias and bst2. connect a ceramic capacitor between bst2 and lx2. see the high-side gate-driver supply (bst_) section. 33 fselbst frequency select pin for the preboost. when pulled low, the preboost will have the same switching frequency as buck 1. when pulled high, the preboost will have a switching frequency that is 1/5th that of buck 1. fselbst is only active for the MAX16930. fselbst should be connected to ground for the max16931. 34 bston preboost on-indicator output. to obtain a logic signal, pull up bston with an external resistor connected to a positive voltage lower than 5.5v. bston goes high to indicate that the preboost is on. 35 en2 high-voltage tolerant, active-high digital enable input for buck 2. driving en2 high enables buck 2. 36 en1 high-voltage tolerant, active-high digital enable input for buck 1. driving en1 high enables buck 1. 37 en3 high-voltage tolerant, active-high digital enable input for preboost. when en3 is high, the external preboost is enabled and begins switching if v ins drops below v ins,olv and required conditions are met (see the preboost section). 39 bst1 boost capacitor connection for high-side gate voltage of buck 1. connect a high-voltage diode between bias and bst1. connect a ceramic capacitor between bst1 and lx1. see the high-side gate-driver supply (bst_) section. 40 dh1 high-side gate-drive output for buck 1. dh1 output voltage swings from v lx1 to v bst1 . ep exposed pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to pgnd1, pgnd2, pgnd3, and agnd. the exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the ic. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
13 detailed description the MAX16930/max16931 are automotive-rated triple- output switching power supplies. these devices inte - grate two synchronous step-down controllers and an asynchronous step-up controller and can provide up to three independently controlled power rails as follows: ? a preboost with adjustable output voltage. ? a buck controller with a fixed 5v output voltage or an adjustable 1v to 10v output voltage. ? a buck controller with a fixed 3.3v output voltage or an adjustable 1v to 10v output voltage. the buck controllers and the preboost can each provide up to 10a output current and ar independently control - lable. buck 1, buck 2, and the preboost are enabled and disabled by the en1, en2, and en3 control inputs, respectively. these are active-high inputs and can be connected directly to car battery. ? en1 and en2 enable the respective buck controllers. connect en1 and en2 directly to v bat or to power- supply sequencing logic. ? en3 controls the boost controller in standby mode (only buck 2 is active), the total supply current is reduced to 30a (typ). when all three con - trollers are disabled, the total current drawn is further reduced to 6.8a. fixed 5v linear regulator (bias) the internal circuitry of the MAX16930/max16931 requires a 5v bias supply. an internal 5v linear regulator (bias) generates this bias supply. bypass bias with a 6.8 f or greater ceramic capacitor to guarantee stability under the full-load condition. the internal linear regulator can source up to 100ma (150ma under extvcc switchover, see the extvcc switchover section). use the following equation to esti - mate the internal current requirements for the MAX16930/ max16931: i bias = i cc + f sw (q g_dl3 + q g_dh1 + q g_dl1 + q g_dh2 + q g_dl2 ) = 10ma to 50ma (typ) where i cc is the internal supply current, 5ma (typ), f sw is the switching frequency, and q g_ is the mosfets total gate charge (specification limits at v gs = 5v). to minimize the internal power dissipation, bypass bias to an external 5v rail. extvcc switchover the internal linear regulator can be bypassed by con - necting an external supply (3v to 5.2v) or the output of one of the buck converters to extvcc. bias inter - nally switches to extvcc and the internal linear regulator turns off. this configuration has several advantages: ? it reduces the internal power dissipation of the MAX16930/max16931. ? the low-load efficiency improves as the internal sup - ply current gets scaled down proportionally to the duty cycle. if v extvcc drops below v th,extvcc = 3.0v (min), the internal regulator enables and switches back to bias. undervoltage lockout (uvlo) the bias input undervoltage lockout (uvlo) circuitry inhibits switching if the 5v bias supply (bias) is below its 2.9v (typ) uvlo falling threshold. once the 5v bias supply (bias) rises above its uvlo rising threshold and en1 and en2 enable the buck controllers, the controllers start switching and the output voltages begin to ramp up using soft-start. buck controllers the MAX16930/max16931 provide two buck controllers with synchronous rectification. the step-down control - lers use a pwm, current-mode control scheme. external logic-level mosfets allow for optimized load-current design. fixed-frequency operation with optimal interleav - ing minimizes input ripple current from the minimum to the maximum input voltages. output-current sensing provides an accurate current limit with a sense resistor or power dissipation can be reduced using lossless current sensing across the inductor. soft-start once a buck converter is enabled by driving the cor - responding en_ high, the soft-start circuitry gradually ramps up the reference voltage during soft-start time (t sstart = 6ms (typ)) to reduce the input surge currents during startup. before the device can begin the soft-start, the following conditions must be met: 1) v bias exceeds the 3.4v (max) undervoltage lockout threshold. 2) v en_ is logic-high. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
14 switching frequency/external synchronization the MAX16930 provides an internal oscillator adjust - able from 1mhz to 2.2mhz. the max16931 provides an internal oscillator adjustable from 200khz to 1mhz. high-frequency operation optimizes the application for the smallest component size, trading off efficiency to higher switching losses. low-frequency operation offers the best overall efficiency at the expense of component size and board space. to set the switching frequency, connect a resistor r fosc from fosc to agnd. see tocs 8 and 9 in the typical operating characteristics section to determine the relationship between switching frequency and r fosc . buck 1 and the boost converter are synchronized with the internal clock-signal rising edge, while buck 2 is synchronized with the clock-signal falling edge. the preboost enables the low-side switch (dl3) with the ris - ing edge of the cycle while buck 1 turns on its high-side n-channel mosfet (dh1). the devices can be synchronized to an external clock by connecting the external clock signal to fsync. a rising edge on fsync resets the internal clock. keep the fsync frequency between 110% and 125% of the internal frequency. the fsync signal should have a 50% duty cycle. light-load efficiency skip mode (v fsync = 0v) drive fsync low to enable skip mode. in skip mode, the devices stop switching until the fb voltage drops below the reference voltage. once the fb voltage has dropped below the reference voltage, the devices begin switching until the inductor current reaches 30% (skip threshold) of the maximum current defined by the inductor dcr or output shunt resistor. forced-pwm mode (v fsync ) driving fsync high prevents the devices from enter - ing skip mode by disabling the zero-crossing detection of the inductor current. this forces the low-side gate- driver waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor cur - rent reverses at light loads and discharges the output capacitor. the benefit of forced pwm mode is to keep the switching frequency constant under all load conditions. however, forced-frequency operation diverts a consider - able amount of the output current to pgnd, reducing the efficiency under light-load conditions. forced-pwm mode is useful for improving load-transient response and eliminating unknown frequency harmonics that can interfere with am radio bands. spread spectrum the MAX16930agls/MAX16930aglu/max16931agls feature enhanced emi performance. they perform q 6% dithering of the switching frequency to reduce peak emission noise at the clock frequency and its harmonics, making it easier to meet stringent emission limits. when using an external clock source (i.e., driving the fsync input with an external clock), spread spectrum is disabled. buck 2 switching frequency for the MAX16930atlt and MAX16930atlu, the switch - ing frequency of buck 2 is set to 1/2 of f sw (buck 1 switch - ing frequency). when using these devices, the external components of buck 2 should be sized to account for the reduced switching frequencies (see the design procedure section). mosfet gate drivers (dh_ and dl_) the dh_ high-side n-channel mosfet drivers are pow - ered from capacitors at bst_ while the low-side drivers (dl_) are powered by the 5v linear regulator (bias). on each channel, a shoot-through protection circuit monitors the gate-to-source voltage of the external mosfets to prevent a mosfet from turning on until the complemen - tary switch is fully off. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the protection circuits to work properly. follow the instructions listed to provide the necessary low- resistance and low-inductance path: ? use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). it may be necessary to decrease the slew rate for the gate drivers to reduce switching noise or to compensate for low-gate charge capacitors. for the low-side drivers, use gate capacitors in the range of 1nf to 5nf from dl_ to gnd. for the high-side drivers, connect a small 5 i to 10 i resistor between bst_ and the bootstrap capacitor. note: gate drivers must be protected during shutdown, at the absence of the supply voltage (v bias = 0v) when the gate is pulled high either capacitively or by the leak - age path on the pcb. therefore, external gate pulldown resistors are needed, especially at dl3 to prevent mak - ing a direct path from v bat to gnd. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
15 high-side gate-driver supply (bst_) the high-side mosfet is turned on by closing an inter - nal switch between bst_ and dh_ and transferring the bootstrap capacitors (at bst_) charge to the gate of the high-side mosfet. this charge refreshes when the high-side mosfet turns off and the lx_ voltage drops down to ground potential, taking the negative terminal of the capacitor to the same potential. at this time the bootstrap diode recharges the positive terminal of the bootstrap capacitor. the selected n-channel high-side mosfet determines the appropriate boost capacitance values (c bst_ in the typical operating circuit ) according to the following equation: = ? g bst_ bst_ q c v where q g is the total gate charge of the high-side mosfet and d v bst_ is the voltage variation allowed on the high-side mosfet driver after turn-on. choose d v bst_ such that the available gate-drive voltage is not significantly degraded (e.g., d v bst_ = 100mv to 300mv) when determining c bst_ . the boost capacitor should be a low-esr ceramic capacitor. a minimum value of 100nf works in most cases. current limiting and current-sense inputs (out_ and cs_) the current-limit circuit uses differential current-sense inputs (out_ and cs_) to limit the peak inductor current. if the magnitude of the current-sense signal exceeds the current-limit threshold (v limit1,2 = 80mv (typ)), the pwm controller turns off the high-side mosfet. the actual maximum load current is less than the peak current- limit threshold by an amount equal to half of the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out_ /v in ). for the most accurate current sensing, use a current- sense shunt resistor (r sh ) between the inductor and the output capacitor. connect cs_ to the inductor side of r sh and out_ to the capacitor side. dimension r sh such that the maximum inductor current (i l,max = i load,max +1/2 i ripple,pp ) induces a voltage of v limit1,2 across r sh including all tolerances. for higher efficiency, the current can also be measured directly across the inductor. this method could cause up to 30% error over the entire temperature range and requires a filter network in the current-sense circuit. see the current-sense measurement section. voltage monitoring (pgood_) the MAX16930/max16931 include several power moni - toring signals to facilitate power-supply sequencing and supervision. pgood_ can be used to enable circuits that are supplied by the corresponding voltage rail, or to turn on subsequent supplies. each pgood_ goes high (high impedance) when the corresponding regulator output voltage is in regulation. each pgood_ goes low when the corresponding regula - tor output voltage drops below 15% (typ) or rises above 15% (typ) of its nominal regulated voltage. connect a 10k i (typ) pullup resistor from pgood_ to the relevant logic rail to level-shift the signal. pgood_ asserts low during soft-start, soft-discharge, and when either buck converter is disabled (either en1 or en2 is low). supply monitoring (ins) the supply voltage in automotive systems can vary sig - nificantly and indicate potentially dangerous situations for the application. undervoltage transients can indicate impending loss of power (for example during engine-start with a weak battery), while overvoltage conditions can quickly exceed the thermal budget of the application. the devices include a dedicated battery voltage sensor at ins to quickly detect overvoltage and undervoltage for the boost converter. connect ins to the center tap of a resistive divider from the input voltage (battery) to term to set the threshold voltage for v ins,off, v ins,on,sw, and v ins,uv . for example, with a 153k i /1% resistor between ins and v bat and a 20k i /1% resistor between ins and term, the following typical automotive v bat levels can be sensed, allowing for proper turn-on/turn-off of the pre - boost. if this setting is not sufficient, optimize the divider for the most critical level. signal v bat(min) (v) v bat(typ) (v) v bat(max) (v) v ins,off 10.38 10.81 11.25 v ins,on,sw 9.515 9.95 10.38 v ins,uv rising 2.81 3.0275 3.24 v ins,uv falling 2.38 2.6 2.81 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
16 preboost the MAX16930/max16931 include an asynchronous current-mode preboost with adjustable output. this pre - boost can be used independently, but is ideally suited for applications that need to stay fully functional during input voltage dropouts typical for automotive cold-crank or start-stop. the preboost is turned on by bringing en3 high. en3 can be used for power-supply sequencing and implementing a boost timeout to prevent overheating the components used for the boost converter. while the boost circuit is essential to maintain func - tionality during undervoltage events, it reduces system efficiency. during normal operation, the boost diode dis - sipates power and the resistive dividers at ins and fb3 sink significant amounts of quiescent current. increasing the efficiency of the boost circuit (term) the MAX16930/max16931 provide a feature to improve the efficiency of the boost circuit when it is not active: ? term provides a switch to gnd for the ins and fb3 voltage-dividers. this switch opens during standby mode and shutdown mode to reduce the quiescent current by 240a, assuming that resistors used in the voltage-divider network are in the range of 100k i . preboost n-channel mosfet driver (dl3) dl3 drives the gate of an external n-channel mosfet. the driver is powered by the 5v (typ) internal regulator (bias) or the external bypass supply (evtvcc). dl3 asserts low during standby mode. switching frequency in boost controller the preboost switching frequency (f boost ) is derived from the buck controllers switching frequency (f sw ) by set - ting fosc. see the electrical characteristics table. on the MAX16930, f boost can be set equal to f sw by connecting fbstsel to ground or to 1/5fsu by connecting fbstsel to bias. the gate driver of the preboost turns on simul - taneously with the high-side driver of buck 1. fselbst should be connected to ground on the max16931. current limit in boost controller a current-sense resistor (r cs ), connected cs3p and cs3n, sets the current limit of the boost converter. the cs input has a voltage trip level (v cs ) of 120mv (typ). the low 120mv current-limit threshold reduces the power dissipation in the current-sense resistor. use a current- sense filter to reduce capacitive coupling during turn on. see the shunt resistor selection in boost converter section. thermal-overload, overcurrent, and overvoltage and undervoltage behavior thermal-overload protection thermal-overload protection limits total power dissipation in the devices. when the junction temperature exceeds +170 n c, an internal thermal sensor shuts down the devices, allowing them to cool. the thermal sensor turns on the devices again after the junction temperature cools by 20 n c. overcurrent protection if the inductor current on the MAX16930 and max16931 exceed the maximum current limit programmed at cs_ and out_, the respective driver turns off. in an overcurrent mode, this results in shorter and shorter high- side pulses. a hard short results in a minimum on-time pulse every clock cycle. choose the components so they can withstand the short- circuit current if required. overvoltage protection the devices limit the output voltage of the buck convert - ers by turning off the high-side gate driver at approxi - mately 115% of the regulated output voltage. the output voltage needs to come back in regulation before the high-side gate driver starts switching again. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
17 design procedure buck converter design procedure effective input voltage range in buck converters although the MAX16930/max16931 can operate from input supplies up to 36v (42v transients) and regulate down to 1v, the minimum voltage conversion ratio (v out / v in ) might be limited by the minimum controllable on-time. for proper fixed-frequency pwm operation and optimal efficiency, buck 1 and buck 2 should operate in continu - ous conduction during normal operating conditions. for continuous conduction, set the voltage conversion ratio as follows: > out on(min) sw in v t f v where t on(min) is 50ns (typ) and f sw is the switching frequency in hz. if the desired voltage conversion does not meet the above condition, pulse skipping occurs to decrease the effective duty cycle. decrease the switching frequency if constant switching frequency is required. the same is true for the maximum voltage conversion ratio. the maximum voltage conversion ratio is limited by the maximum duty cycle (95%). < ? out in drop v 0.95 vv where v drop = i out (r on,hs + r dcr ) is the sum of the parasitic voltage drops in the high-side path and f sw is the programmed switching frequency. during low drop operation, the devices reduce f sw to 25% (max) of the programmed frequency. in practice, the above condition should be met with adequate margin for good load-tran - sient response. setting the output voltage in buck converters connect fb1 and fb2 to bias to enable the fixed buck controller output voltages (5v and 3.3v) set by a preset internal resistive voltage-divider connected between the output (out_) and agnd. to externally adjust the output voltage between 1v and 10v, connect a resistive divider from the output (out_) to fb_ to agnd (see the typical operating circuit . calculate r fb_1 and r fb_2 with the fol - lowing equation: ?? ?? = ? ?? ?? ?? ?? ?? ?? out_ fb_1 fb_2 fb_ v rr 1 v where v fb_ = 1v (typ) (see the electrical characteristics table). dc output accuracy specifications in the electrical characteristics table refer to the error comparators threshold, v fb_ = 1v (typ). when the inductor conducts continuously, the devices regulate the peak of the output ripple, so the actual dc output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. in discontinuous conduction mode (skip or stdby active and i out < i load(skip) ), the devices regulate the valley of the output ripple, so the output voltage has a dc regu - lation level higher than the error-comparator threshold. inductor selection in buck converters three key inductor parameters must be specified for operation with the MAX16930/max16931: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). to determine the optimum induc - tance, knowing the typical duty cycle (d) is important. = = ?+ out out in in out ds(on) dcr vv d or d v v i (r r ) if the r dcr of the inductor and r ds(on) of the mosfet are available with v in = (v bat - v diode ). all values should be typical to optimize the design for normal operation. inductance the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, efficiency, and transient response requirements. ? lower inductor values increase lir, which minimizes size and cost and improves transient response at the cost of reduced efficiency due to higher peak currents. ? higher inductance values decrease lir, which increases efficiency by reducing the rms current at the cost of requiring larger output capacitors to meet load-transient specifications. the ratio of the inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good initial value is a 30% peak-to-peak ripple current to aver - age-current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir then determine the inductor value as follows: in out sw out (v v )xd l[h] f [mhz]x i x lir ? = where v in , v out , and i out are typical values (so that efficiency is optimum for typical conditions). MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
18 peak inductor current inductors are rated for maximum saturation current. the maximum inductor current equals the maximum load cur - rent in addition to half of the peak-to-peak ripple current: ? = + inductor peak load(max) i ii 2 for the selected inductance value, the actual peak-to-peak inductor ripple current ( d i inductor ) is calculated as: ? ?= out in out inductor in sw v(vv) i v xf xl where d i inductor is in ma, l is in h, and f sw is in khz. once the peak current and the inductance are known, the inductor can be selected. the saturation current should be larger than i peak or at least in a range where the inductance does not degrade significantly. the mosfets are required to handle the same range of current without dissipating too much power. mosfet selection in buck converters each step-down controller drives two external logic-level n-channel mosfets as the circuit switch elements. the key selection parameters to choose these mosfets include the items in the following sections. threshold voltage all four n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. if the internal regulator is bypassed (for example: v extvcc = 3.3v), then the n-channel mosfets should be chosen to have guaranteed on-resistance at that gate-to-source voltage. maximum drain-to-source voltage (v ds(max) ) all mosfets must be chosen with an appropriate v ds rating to handle all v in voltage conditions. current capability the n-channel mosfets must deliver the average cur - rent to the load and the peak current during switching. choose mosfets with the appropriate average current at v gs = 4.5v or v gs = v extvcc when the internal linear regulator is bypassed. for load currents below approxi - mately 3a, dual mosfets in a single package can be an economical solution. to reduce switching noise for smaller mosfets, use a series resistor in the bst_ path and additional gate capacitance. contact the factory for guidance using gate resistors. current-sense measurement for the best current-sense accuracy and overcur - rent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 1a . this configuration constantly monitors the inductor current, allowing accurate current-limit pro - tection. use low-inductance current-sense resistors for accurate measurement. alternatively, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series rc circuit across the inductor ( figure 1b ) with an equivalent time constant: ?? = ?? + ?? 2 cshl dcr 12 r rr rr and: ?? = + ?? ?? dcr eq 1 l 11 r c r r2 where r cshl is the required current-sense resistor and r dcr is the inductors series dc resistor. use the induc - tance and r dcr values provided by the inductor manufacturer. carefully observe the pcb layout guidelines to ensure the noise and dc errors do no corrupt the differential current-sense signals seen by cs_ and out_. place the sense resistor close to the devices with short, direct traces, making a kelvin-sense connection to the current- sense resistor. input capacitor in buck converters the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage ripple within design requirements. the 180 ripple phase operation increases the frequency of the input capacitor ripple current to twice the individual converter switching fre - quency. when using ripple phasing, the worst-case input capacitor ripple current is when the converter with the highest output current is on. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
19 the input voltage ripple is composed of d v q (caused by the capacitor discharge) and d v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of d v q and d v esr that peaks at the end of an on-cycle. calculate the input capacitance and esr required for a specific ripple using the following equation: ( ) esr pp load(max) out load(max) in in q sw v esr[ ] i i 2 v ix v c [f] v xf ? ? ?= ? ?? + ?? ?? ?? ?? ?? ?? = ? where: ( ) ? ? ?= in out out pp in sw v v xv i v xf xl i load(max) is the maximum output current in a, d i p-p is the peak-to-peak inductor current in a, f sw is the switch - ing frequency in mhz, and l is the inductor value in h. the internal 5v linear regulator (bias) includes an output uvlo with hysteresis to avoid unintentional chattering during turn-on. use additional bulk capacitance if the input source impedance is high. at lower input voltage, additional input capacitance helps avoid possible under - shoot below the undervoltage lockout threshold during transient loading. figure 1. current-sense configurartions c out c out c in c in l nl nh input (v in ) a) output series resistor sensing dh_ lx_ dl_ gnd cs_ out_ l nl nh r2 c eq dcr r1 input (v in ) b) lossless inductor sensing dh_ lx_ dl_ gnd cs_ out_ inductor r cshl = ( ) r dcr r2 r1 + r2 r dcr = [ + ] 1 r1 1 r2 l c eq MAX16930 / max16931 MAX16930/ max16931 r sense MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
20 output capacitor in buck converters the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. the capacitor is usually selected by esr and the voltage rating rather than by capacitance value. when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from caus - ing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the transient considerations sec - tion). however, low-capacity filter capacitors typically have high-esr zeros that can affect the overall stability. the total voltage sag (v sag ) can be calculated as follows: ? = ? ? ?? + 2 load(max) sag out in max out load(max) out l( i ) v 2c ((v d ) v ) i (t t) c the amount of overshoot (v soar ) during a full-load to no-load transient due to stored inductor energy can be calculated as: ? 2 load(max) soar out out (i )l v 2c v esr considerations the output filter capacitor must have low enough equivalent series resistance (esr) to meet output rip - ple and load-transient requirements, yet have high enough esr to satisfy stability requirements. when using high-capacitance, low-esr capacitors, the filter capaci - tors esr dominates the output-voltage ripple. so the output capacitors size depends on the maximum esr required to meet the output-voltage ripple (v ripple(p-p) ) specifications: ? = ripple(p p) load(max) v esr x i x lir in standby mode, the inductor current becomes discon - tinuous, with peak currents set by the idle-mode current- sense threshold (v cs,skip = 26mv (typ)). transient considerations the output capacitor must be large enough to absorb the inductor energy while transitioning from no-load to full-load condition without tripping the overvoltage fault protection. the total output-voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur. therefore: ( ) ( ) ? = ? ? ?? + 2 load(max) out sag in max out load(max) sag li c 2v (v xd v ) i tt v where d max is the maximum duty factor (approximately 95%), l is the inductor value in h, c out is the output capacitor value in f, t is the switching period (1/f sw ) in s, and d t equals (v out /v in ) x t. the MAX16930/max16931 use a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the controller uses the voltage drop across the dc resistance of the inductor or the alternate series current- sense resistor to measure the inductor current. current- mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor result - ing in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. a single series resistor (r c ) and capacitor (c c ) is all that is required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for out - put filtering (see figure 2 ). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a non-ceramic output capacitor loop, add another compensation capacitor (c f ) from comp to agnd to cancel this esr zero. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
21 the basic regulator loop is modeled as a power modula - tor, output feedback divider, and an error amplifier as shown in figure 2 . the power modulator has a dc gain set by g mc x r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. the loop response is set by the following equations: mod(dc) mc load gain g r = where r load = v out /i lout(max) in i and g mc =1/(a v_ cs x r dc ) in s. a v_cs is the voltage gain of the current- sense amplifier and is typically 11v/v. r dc is the dc resistance of the inductor or the current-sense resistor in i . in a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the following frequency: pmod out load 1 f 2c r = the unity gain frequency of the power stage is set by c out and g mc : mc ugainpmod out g f 2c = the output capacitor and its esr also introduce a zero at: zmod out 1 f 2 esr c = when c out is composed of n identical capacitors in parallel, the resulting c out = nxc out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb / v out , where v fb is 1v (typ). the transconductance error amplifier has a dc gain of gain ea(dc) = g m,ea x r out,ea , where g m,ea is the error amplifier transconductance, which is 1200s (typ), and r out,ea is the output resistance of the error amplifier, which is 30m i (typ) (see the electrical characteristics table.) a dominant pole (f dpea ) is set by the compensa - tion capacitor (c c ) and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c , where the loop gain equals 1 (0db)). thus: dpea c o u t ,e a c 1 f 2 c (r r ) = + zea cc 1 f 2c r = pea fc 1 f 2cr = the loop-gain crossover frequency (f c ) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (f pmod ). select a value for f c in the range: << sw pmod c f ff 5 figure 2. compensation network cs _ out_ fb_ r 1 r esr c c c f r c r 2 v ref c out g mc = 1/(a vc s x r dc ) current mode powe r modulatio n erro r am p co mp _ g mea = 1200 s 30 mi MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
22 at the crossover frequency, the total loop gain must be equal to 1. so: cc fb mod(f ) ea(f ) out v gain gain 1 v = c ea(f ) m,ea c gain g r = c pmod mod( f ) mod(dc) c f gain gain f = therefore: c fb mod( f ) m,ea c out v gain g r 1 v = solving for r c : c out c m,ea fb mod( f ) v r g v gain = set the error-amplifier compensation zero formed by r c and c c at the f pmod . calculate the value of c c as follows: c 1 c 2f r pmod c = if f zmod is less than 5 x f c , add a second capacitor c f from comp to agnd. the value of c f is: f 1 c 2f r zmod c = as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accord - ingly and the crossover frequency remains the same. below is a numerical example to calculate the compen - sation network component values of figure 2 : a v_cs = 11v/v r dcr = 15m i g mc = 1/(a v_cs x r dc ) = 1/(11 x 0.015) = 6.06 v out = 5v i out(max) = 5.33a r load = v out /i out(max) = 5v/5.33a = 0.9375 i c out = 2x47f = 94f esr = 9m i /2 = 4.5m i f sw = 26.4/65.5k i = 0.403mhz == mod(dc) gain 6.06 0.9375 5.68 pmod 1 f 1.8khz 2 94f 0.9375 = << sw pmod c f ff 5 c 1.8khz f 80.6khz << select f c = 40khz zmod 1 f 376khz 2 4.5m 94f = ? since f zmod >f c : r c 16k i c c 5.6nf c f 27pf boost converter design procedure setting the output voltage in boost converter adjust the boost converter output voltage by connecting a resistive divider from the output of the boost converter to fbbst to term ( figure 3 ) and r b2 (fb3 to term resistor). calculate r b1 (v out(boost) to fbbst resistor) using the following equation: ?? ?? = ? ?? ?? ?? ?? ?? ?? out(boost b1 b2 fb3 v) rr 1 v where v fb3 = 1.2v (typ) (see the electrical characteristics table). figure 3. boost converter adjustable output voltage r b1 r b2 v out(boost) term fb3 MAX16930 / max16931 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
23 inductor selection in boost converter duty cycle and frequency are important to calculate the inductor size, as the inductor current ramps up during the on-time of the switch and ramps down during its off- time. a higher switching frequency generally improves transient response and reduces component size. however, if the boost components are to be used as the input filter components during nonboost operation, a low frequency is advantageous. the boost frequency is selected as a multiple of the buck frequency by setting the input voltage of fselbst. ? if v fselbst =v gnd , then f boost = f sw ? if v fselbst = v bias , then f boost = 1/5f sw the duty-cycle range of the boost converter depends on the effective input to output-voltage ratio. in the following calculations, the duty cycle refers to the on-time of the boost mosfet: ? = out(max) bat(min) max out(max) vv d v or including the voltage drops across the inductor, mosfet (v on,fet ), and the boost diode (v d ): ? ++ = out(max) bat(min) d out dc max out(max) v v v (i xr ) d v in some applications, it may be beneficial to maintain discontinuous conduction (dcm) in the boost converter under all conditions. this formula defines the maximum size of the inductor for dcm mode: l max < v in(min) x d max /(2 x (i out(max) /1 - d max )) x f sw(min) the ratio of the inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good initial value is a 30% peak-to-peak ripple current to aver - age-current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir determine the inductor value as follows: = in sw vd l[h] f [mhz] lir where: v in = typical input voltage v out = typical output voltage lir = 0.3 x i out /1 - d. select the inductor with a saturation current rating higher than the peak switch current limit of the converter: ? >+ l,rip,max l,peak l,max i ii 2 running a boost converter in continuous conduction mode introduces a right-half plane zero into the transfer function, which can only be compensated by reducing bandwidth in the voltage feedback loop by adding a capacitor across the low-side feedback resistor. this results in a system that is slow to respond to load and line changes. if the boost converter response is too slow, increase the ripple current. a smaller inductor and higher frequency generally improves the preboost, especially for high input to output ratios. mosfet selection in boost converter the key selection parameters to choose the n-channel mosfet used in the boost converter are as follows. threshold voltage the boost n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. maximum drain-to-source voltage (v ds(max) ) the mosfet must be chosen with an appropriate v ds rating to handle all v in voltage conditions. current capability the n-channel mosfet must deliver the input current (i in(max) ): = ? max in(max) load(max) max d ii x 1d choose mosfets with the appropriate average current at v gs = 4.5v. diode selection in boost converter the diode must deliver the average output current (i out ) plus the peak inductor current (i lpeak ). the boost diode current can be higher during nonboost operation when it supplies current to both buck converters under full-load conditions. use a boost diode with a power dissipation of p = i out x v diode or higher. to reduce the power dissipation, use a schottky diode. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
24 input capacitor selection in boost converter the input current for the boost converter is continuous and the rms ripple current at the input capacitor is low. calculate the minimum input capacitor value and maxi - mum esr using the following equations: ? = ? ? = ? l bat sw q esr l i xd c 4xf x v v esr i where: ? ?= bat ds l sw (v v )xd i lxf v ds is the total voltage drop across the external mosfet plus the voltage drop across the inductor esr. d i l is peak-to-peak inductor ripple current as calculated above. d v q is the portion of input ripple due to the capacitor discharge and d v esr is the contribution due to esr of the capacitor. assume the input capacitor ripple contri - bution due to esr ( d v esr ) and capacitor discharge ( d v q ) are equal when using a combination of ceramic and aluminum capacitors. during the converter turn-on, a large current is drawn from the input source especially at high output-to-input differential. output capacitor selection in boost converter in a boost converter, the output capacitor supplies the load current when the boost mosfet is on. the required output capacitance is high, especially at higher duty cycles. also, the output capacitor esr needs to be low enough to minimize the voltage drop while supporting the load current. use the following equations to calculate the output capacitor for a specified output ripple. all ripple values are peak-to-peak. ? = = ? esr out out max out q sw v esr i i xd c v xf i out is the load current in a, f sw is in mhz, c out is f, d v q is the portion of the ripple due to the capacitor dis - charge, and d v esr is the contribution due to the esr of the capacitor. d max is the maximum duty cycle at the minimum input voltage. use a combination of low-esr ceramic and high-value, low-cost aluminum capacitors for lower output ripple and noise. shunt resistor selection in boost converter the current-sense resistor (r cs ), connected between the battery and the inductor, sets the current limit. the cs input has a voltage trip level (v cs ) of 120mv (typ). set the current-limit threshold high enough to accommo - date the component variations. use the following equa - tion to calculate the value of r cs : = cs cs in(max) v r i where i in(max) is the peak current that flows through the mosfet at full load and minimum v in . i in(max) = i load(max) /(1 - d max ) when the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator threshold, the mosfet driver (dl3) quickly terminates the on-cycle. MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
25 applications information layout recommendations careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention ( figure 4 ). if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full load efficiency by 1% or more. ? minimize current-sensing errors by connecting cs_ and out_. use kelvin sensing directly across the current-sense resistor (rsense_). ? route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (fb_, cs_, and out_). layout procedure 1) place the power components first, with ground ter - minals adjacent (low-side fet, cin, cout_, and schottky). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite nl_ and nh_ to keep lx_, gnd, dh_, and the dl_ gate drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adap - tive dead-time sensing. 3) group the gate-drive components (bst_ diode and capacitor and ldo bypass capacitor bias) together near the controller ic. be aware that gate currents of up to 1a flow from the bootstrap capacitor to bst_, from dh_ to the gate of the external hs switch and from the lx_ pin to the inductor. up to 100ma of cur - rent flow from the bias capacitor through the boot - strap diode to the bootstrap capacitor. dimension those traces accordingly. 4) make the dc-dc controller ground connections as shown in figure 4 . this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an ana - log ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly under the ic. 5) connect the output power planes directly to the out - put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. figure 4. layout example inductor c out c out c in input kelvin-sense vias under the sense resistor (refer to the evaluation kit) ground output low-side n-channel mosfet (nh) high-side n-channel mosfet (nl) MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
26 block diagram eamp1 pgood comp pgood1 comp1 pgood low level pgood high level fb1 out1 cs1 en1 80 mv(typ) max differential input cs3p bston cs3n fb3 term 50 mv(typ) max different input feedback select logic ref = 1v current limit threshold oscillator tied high (pwm mode) tied low (skip mode) clk2 vin clk1 internal soft start slope comp logic clk 180 out of phase internal linear regulator switchover slope comp logic dc-dc3 control logic dc-dc1 control logic boost en flag zero cross comp csa1 csa3 ref3 = 1.25v en3 ep eamp3 pwm3 cl current limit threshold low gain eamp, no comp pin required cl3 pwm1 lx1 lx2 lx1 bias clk1 step-down dc-dc1 gate drive logic en1 bst1 dh1 lx1 dl1 pgnd1 pgnd2 bias extvcc if 3.1v < v extvcc < 5.2v pwm1 zx1 spread spectrum option available with internal clock only external clock input fsync select logic dc-dc2 control logic same as dc-dc1 above fsync fosc comp2 ins fb2 out2 cs2 en2 pgood2 agnd clk2 step-down dc-dc2 gate drive logic en2 bst2 dh2 lx2 dl2 pwm2 zx2 lx2 in vin step-up dc-dc3 gate drive logic boost enabled pgnd3 dl3 bias pwm3 clk3 en3 en goes high check for ins thresholds boost enabled clk3 clk1 if low, clk3 = clk1 if high, clk3 = clk1/5 fselbst fselbst input tied low tied high pre-bst sns threshold comparator start-up turn on threshold boost on-off thresholds uvlo threshold MAX16930 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
27 typical operating circuit MAX16930 max16931 in term in in out2 term v bat bias pgnd1 in fb3 pgnd3 en3 ins in term cs3p cs3n dl3 en1 dl1 bst1 lx1 dh1 pgood1 comp1 fb1 cs1 out1 fselbs t bsto n n.c. pgnd2 bst2 lx2 dh2 en2 pgood2 extvcc fb2 cs2 out2 comp2 n.c. fsync agnd fosc out1 bias bias bias dl2 out1 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
28 ordering information selector guide note: insert the desired suffix letter (from selector guide ) into the blank to indicate buck 2 switching frequency and spread spectrum. /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * future product. * * exposed pad side-wettable flanked package. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrate d.com/ packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos part temp range pin-package MAX16930 atl_/v+ -40c to +125c 40 tqfn-ep** max16931 atl_/v+* -40c to +125c 40 tqfn-ep** part buck 1 switching frequency (f sw1 ) buck 2 switching frequency (f sw2 ) spread spectrum (%) MAX16930 atlr/v+ 1mhz to 2.2mhz f sw1 MAX16930atls/v+ 1mhz to 2.2mhz f sw1 6 MAX16930atlt/v+ 1mhz to 2.2mhz 1/2f sw1 MAX16930atlu/v+ 1mhz to 2.2mhz 1/2f sw1 6 max16931 atlr/v+ 200khz to 1mhz f sw1 max16931atls/v+ 200khz to 1mhz f sw1 6 package type package code outline no. land pattern no. 40 tqfn-ep t4066+5 21-0141 90-0055 MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 29 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/13 initial release MAX16930/max16931 2mhz, 36v, dual buck with preboost and 20a quiescent current

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